The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit that incorporates a built-in self test circuit of a memory and performs a fault diagnosing operation by using this circuit.
There is a method that detects a defective chip by performing a built-in self test (to be referred to as a BIST hereinafter) by using a BIST circuit incorporated into a semiconductor integrated circuit including a memory, and diagnoses faults in the defective chip by using the BIST circuit, thereby extracting candidates of defective portions of the memory.
Examples of the BIST circuit are a comparator type BIST circuit and compaction type BIST circuit. The comparator type BIST circuit compares an expected value equal to written data with data read out from a memory, and determines the presence/absence of faults. The compaction type BIST circuit compresses data read out from a memory in the BIST circuit, and determines the presence/absence of faults by using the compressed data.
First, the BIST operation of a conventional semiconductor integrated circuit having the comparator type BIST circuit will be described below.
A BIST controller in the BIST circuit controls a data generator, address generator, and control signal generator. A block called a memory collar includes a memory as an object of the BIST together with logic elements necessary for the BIST operation.
The memory receives write data generated by the data generator, address data generated by the address generator, and a control signal generated by the control signal generator.
A capture register on the output side of the memory temporarily holds output data from the memory. A comparator compares the output from the capture register with a data expected value generated by the data generator. A flag register holds the comparison result. A result analyzer in the BIST circuit receives the output from the flag register, and outputs the final BIST result.
When one BIST circuit performs the BIST on a plurality of memories, the result analyzer receives individual flag data, checks the overall BIST result, and outputs the final BIST result.
The BIST operation of a conventional semiconductor integrated circuit having the compaction type memory BIST circuit will be described below.
Similar to the semiconductor integrated circuit having the comparator type memory BIST circuit, a BIST controller in the BIST circuit controls a data generator, address generator, and control signal generator. A memory collar includes a memory as an object of the BIST.
The memory receives write data generated by the data generator, address data generated by the address generator, and a control signal generated by the control signal generator. A compactor receives the output from the memory, and sequentially compresses the input data.
An example of the structure of the compactor is described in non-patent reference 1 (to be described later). An MISR (Multiple Input Signature Register) as a modification of a linear feedback shift register is generally used.
At the end of the BIST, the value saved in the compactor is compared as the BIST result with a precalculated expected value, thereby determining if the memory is fault-free or not.
When diagnosing memory faults by using the BIST circuit in order to extract candidates of fault portions of the memories, output data from a plurality of memories are sequentially serially extracted outside and observed by an external tester.
When using the comparator type BIST circuit described above, capture registers that capture the outputs from memories in individual memory collars and flag registers that receive the outputs from comparators in the memory collars are connected in series. This series circuit, an address register that receives addresses from address generators in the individual BIST circuits, and a flag register of the overall circuit are connected in series, thereby forming one circular shift path as a whole.
This shift path is used to diagnose memories; the shift path shifts and outputs the values of the individual registers in synchronism with the read timing. Since the shift path is circularly formed, the circuit can return to the BIST operation interrupted state at the end of the shift output.
Then, the shift path resumes the BIST, and shifts and outputs the values of the registers at the next read timing. The internal state of the memory can be read out by thus repeating the interruption of the BIST operation, the shift output, and the resumption of the BIST operation. On the basis of the obtained results, a fail bitmap indicating fault bit positions in the cell array of the memory is formed, and faults are analyzed.
In the conventional method as described above, however, all the BIST results must be serially read out, so the outputs from memories that are not objects of the fault diagnosis must also be shifted and output. Accordingly, the BIST time very prolongs if one BIST circuit performs the BIST on many memories.
In addition, when the BIST results are shifted and output, it is necessary to observe the shift outputs and compare them with the expected value by using an external tester. Therefore, the operation is limited by the operating speed of the external tester that is lower than the system operating speed of a semiconductor integrated circuit. This makes it difficult to diagnose a fault at the system operating speed of a semiconductor integrated circuit. Consequently, detectable fault candidates cannot be detected only when the fault diagnosis is performed at the system operating speed.
The reference disclosing the MISR as a modification of a linear feedback shift register is as follows.
Built-In Test for VLSI: Pseudo Random Techniques, Paul H. Bardell, William H. MacAnney and Jacob Savir, John Wiley & Sons, 1987